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| 3 volt intel ? advanced+ boot block flash memory (c3) stacked-chip scale package family datasheet product features the 3 volt intel ? advanced+ boot block flash memory (c3) stacked-chip scale package (stacked-csp) device delivers a feature-rich solution for low-power applications. the c3 stacked-csp memory device incorporates flash memory and static ram in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. the c3 stacked-csp memory device offers a protection register and flexible block locking to enable next generation security capability. combined with the intel ? flash data integrator (intel ? fdi) software, the c3 stacked-csp memory device provides a cost-effective, flexible, code plus data storage solution. flash memory plus sram ?reduces memory board space required, simplifying pcb design complexity stacked-chip scale package (stacked- csp) technology ? smallest memory subsystem footprint ?area : 8 x 10 mm for 16mbit (0.13 m) flash + 2mbit or 4mbit sram ?area : 8 x 12 mm for 32mbit (0.13 m) flash + 4mbit or 8mbit sram ? height : 1.20 mm for 16mbit (0.13 m) flash + 2mbit or 4mbit sram and 32mbit (0.13um) flash + 8mbit sram ? height : 1.40 mm for 32mbit (0.13 m) flash + 4mbit sram ?this family also includes 0.25 m and 0.18 m technologies advanced sram technology ? 70 ns access time ? low power operation ? low voltage data retention mode intel ? flash data integrator (fdi) software ? real-time data storage and code execution in the same memory device ? full flash file manager capability advanced+ boot block flash memory ?70 ns access time at 2.7 v ?instant, individual block locking ?128 bit protection register ?12 v production programming ?ultra fast program and erase suspend ? extended temperature ?25 c to +85 c blocking architecture ?block sizes for code + data storage ?4-kword parameter blocks (for data) ? 64-kbyte main blocks (for code) ? 100,000 erase cycles per block low power operation ? async read current: 9 ma (flash) ? standby current: 7 a (flash) ? automatic power saving mode flash technologies ? 0.25 m etox? vi, 0.18 m etox? vii and 0.13 m etox? viii flash technologies ? 28f160xc3, 28f320xc3 252636-001 february, 2003 notice: this document contains information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the lat- est datasheet before finalizing a design.
2 datasheet information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 3 volt intel? advanced+ boot block flash memory stacked-csp family may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. mpeg is an international standard for video compression/decompression promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. additional information on this product family can be obtained by accessing the intel? flash website: http://www.intel.com/design/flash. copyright ? 2003 intel corporation. *other names and brands may be claimed as the property of others. datasheet 3 contents contents 1.0 introduction ............................................................................................................................... .....7 1.1 document conventions ........................................................................................................7 1.2 product overview .................................................................................................................7 1.3 package ballout....................................................................................................................8 1.4 signal definitions ..................................................................................................................9 2.0 principles of operation ...............................................................................................................11 2.1 bus operation.....................................................................................................................1 1 2.1.1 read ...................................................................................................................... 11 2.1.2 output disable .......................................................................................................12 2.1.3 standby..................................................................................................................1 2 2.1.4 flash reset............................................................................................................13 2.1.5 write ..................................................................................................................... .13 3.0 flash memory modes of operation ............................................................................................13 3.1 read array (ffh) ................................................................................................................13 3.2 read identifier (90h) ...........................................................................................................13 3.3 read status register (70h) ................................................................................................14 3.3.1 clear status register (50h) ...................................................................................14 3.4 cfi query (98h) ..................................................................................................................15 3.5 word program (40h/10h) ....................................................................................................15 3.5.1 suspending and resuming program (b0h/d0h)....................................................15 3.6 block erase (20h) ...............................................................................................................16 3.6.1 suspending and resuming erase (b0h/d0h) ........................................................16 3.7 block locking......................................................................................................................18 3.7.1 block locking operation summary........................................................................19 3.7.2 locked state ..........................................................................................................19 3.7.3 unlocked state ......................................................................................................19 3.7.4 lock-down state ...................................................................................................19 3.7.5 reading a block?s lock status ..............................................................................20 3.7.6 locking operation during erase suspend .............................................................20 3.7.7 status register error checking .............................................................................20 3.8 128 bit protection register .................................................................................................21 3.8.1 reading the protection register ............................................................................21 3.8.2 programming the protection register (c0h)..........................................................21 3.8.3 locking the protection register .............................................................................22 4.0 power and reset considerations ..............................................................................................23 4.1 power-up/down characteristics.........................................................................................23 4.2 additional flash features ...................................................................................................23 4.2.1 improved 12 volt production programming ...........................................................23 4.2.2 f-vpp < vpplk for complete protection..............................................................23 5.0 electrical specifications .............................................................................................................24 5.1 absolute maximum ratings ................................................................................................24 5.2 operating conditions ..........................................................................................................25 5.3 capacitance................................................................................................................. .......25 contents 4 datasheet 5.4 dc characteristics.............................................................................................................. 26 5.5 flash ac characteristics. ................................................................................................... 29 5.6 flash ac characteristics?write operations...................................................................... 31 5.7 flash erase and program timings(1)................................................................................. 31 5.8 flash reset operations ...................................................................................................... 34 5.9 sram ac characteristics?read operations.................................................................... 35 5.10 sram ac characteristics?write operations .................................................................... 37 5.11 sram data retention characteristics?extended temperature ....................................... 39 6.0 migration guide information ...................................................................................................... 40 7.0 system design considerations .................................................................................................. 41 7.1 background.................................................................................................................. ....... 41 7.1.1 flash + sram footprint integration ...................................................................... 41 7.1.2 advanced+ boot block flash memory features ................................................... 41 7.2 flash control considerations ............................................................................................. 41 7.2.1 f-rp# connected to system reset....................................................................... 42 7.2.2 f-vcc, f-vpp and f-rp# transition .................................................................... 42 7.3 noise reduction ................................................................................................................. 43 7.4 simultaneous operation ..................................................................................................... 44 7.4.1 sram operation during flash ?busy? ................................................................... 45 7.4.2 simultaneous bus operations ............................................................................... 45 7.5 printed circuit board notes ................................................................................................ 45 7.6 system design notes summary......................................................................................... 45 appendix a program/erase flowcharts ............................................................................................. 46 appendix b cfi query structure ........................................................................................................ 52 appendix c word-wide memory map diagrams ............................................................................... 59 appendix d device id table ................................................................................................................ 62 appendix e protection register addressing ..................................................................................... 63 appendix f mechanical and shipping media details ........................................................................ 64 appendix g additional information .................................................................................................... 68 appendix h ordering information ....................................................................................................... 69 datasheet 5 contents revision history date of revision version description 02/11/03 -001 initial release, stacked-chip scale package contents 6 datasheet 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 7 1.0 introduction this document contains the specifications for the 3volt intel ? advanced+ boot block flash memory (c3) stacked-chip scale package (stacked-csp) device. stacked memory solutions are offered in the following combinations: 32-mbit flash + 8-mbit sram, 32-mbit flash + 4-mbit sram, 16-mbit flash + 4-mbit sram, or 16-mbit flash memory + 2-mbit sram. 1.1 document conventions throughout this document, the following conventions have been adopted. ? voltages: ?2.7 v? refers to the full voltage range, 2.7 v?3.3v; 12 v refers to 11.4 v to 12.6 v ? main block(s) : 32-kword block ? parameter block(s) : 4-kword block 1.2 product overview the c3 stacked-csp device combines flash and sram into a single package, and provides secure low-voltage memory solutions for portable applications. this memory family combines two memory technologies, flash memory and sram, in one package. the flash memory delivers enhanced security features, a block locking capability that allows instant locking/unlocking of any flash block with zero-latency, and a 128-bit protection register that enable unique device identification, to meet the needs of next generation portable applications. improved 12 v production programming can be used to improve factory throughput. the flash memory is asymmetrically-blocked to enable system integration of code and data storage in a single device. each flash block can be erased independently of the others up to 100,000 times. the flash has eight 8-kb parameter blocks located at either the top (denoted by -t suffix) or the bottom (-b suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. the remaining flash memory is grouped into 32-kword main blocks. any individual flash block can be locked or unlocked instantly to provide complete protection for code or data (see section 5.7, ?flash erase and program timings(1)? on page 31 for details). the flash contains both a command user interface (cui) and a write state machine (wsm). the cui serves as the interface between the microcontroller and the internal operation of the flash memory. the internal wsm automatically executes the algorithms and timings necessary for table 1. block organization (x16) memory device kwords 32-mbit flash 2048 16-mbit flash 1024 2-mbit sram 128 4-mbit sram 256 8-mbit sram 512 note: all words are 16 bits each. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 8 datasheet program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. the flash?s status register indicates the status of the wsm by signifying block erase or word program completion and status. flash program and erase automation allows program and erase operations to be executed using an industry-standard two-write command sequence to the cui. program operations are performed in word increments. erase operations erase all locations within a block simultaneously. both program and erase operations can be suspended by the system software in order to read from any other flash block. in addition, data can be programmed to another flash block during an erase suspend. the c3 stacked-csp memory device offers two low-power savings features: automatic power savings (aps) for flash memory and standby mode for flash and sram. the device automatically enters aps mode following the completion of a read cycle from the flash memory. standby mode is initiated when the system deselects the device by driving f-ce# and s-cs1# or s-cs2 inactive. power savings features significantly reduce power consumption. the flash memory can be reset by lowering f-rp# to gnd. this provides cpu-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/-down sequences. 1.3 package ballout 72- notes: 1. flash upgrade balls are shown up to a21 (64-mbit flash) and a22 (128-mbit flash). in all flash and sram combinations, 66 balls are populated on lower density devices. (upper address balls are not populated). ball location a10 is ?nc? on 16/2 devices only. figure 1. 66-ball stacked chip scale package 1 2 3 4 5 6 7 8 a b c d e f g h nc a 20 a 11 a 15 a 14 a 13 a 12 a 16 a 8 a 10 a 9 dq 15 s-we# f-we# nc a 21 dq 13 dq 6 s-v ss f-wp# a 19 dq 11 dq 10 s-lb# s-ub# s-oe# dq 9 dq 8 a 18 a 17 a 7 a 6 a 3 a 2 nc nc a 5 a 4 a 0 f-ce# f-v ss f-rp# a 22 dq 12 s-cs 2 9 10 11 12 f-v ss nc dq 14 dq 7 dq 4 dq 5 dq 2 dq 3 dq 0 dq 1 a 1 s-cs 1 # f-oe# nc nc s-v cc f-v cc top view, balls down f-v ccq f-v pp 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 9 2. to maintain compatibility with all jedec variation b options for this ball location c6, this c6 land pad should be connected directly to the land pad for ball g4 (a17). 1.4 signal definitions table 2. defines the signal definitions shown in the previous ballout. table 2. 3 volt intel ? advanced+ boot block stacked-csp ball descriptions (sheet 1 of 2) symbol type name and function a[20:0] input address inputs for memory addresses. addresses are internally latched during a program or erase cycle. 2-mbit : a[16:0] 4-mbit : a[18:0] 16-mbit : a[19:0] 32-mbit a[20:0] dq[15:0] input / output data inputs/outputs: inputs array data for sram write operations and on the second f-ce# and f-we# cycle during a flash program command. inputs commands to the flash?s command user interface when f-ce# and f-we# are asserted. data is internally latched. outputs array, configuration and status register data. the data balls float to tri-state when the chip is de-selected or the outputs are disabled. f-ce# input flash chip enable: activates the flash internal control logic, input buffers, decoders and sense amplifiers. f-ce# is active low. f-ce# high de-selects the flash memory device and reduces power consumption to standby levels. s-cs1# input sram chip select1: activates the sram internal control logic, input buffers, decoders and sense amplifiers. s-cs1# is active low. s-cs1# high de-selects the sram memory device and reduces power consumption to standby levels. s-cs2 input sram chip select2: activates the sram internal control logic, input buffers, decoders and sense amplifiers. s-cs2 is active high. s-cs2 low de-selects the sram memory device and reduces power consumption to standby levels. f-oe# input flash output enable: enables flash?s outputs through the data buffers during a read operation. f-oe# is active low. s-oe# input sram output enable: enables sram?s outputs through the data buffers during a read operation. s-oe# is active low. f-we# input flash write enable: controls writes to flash?s command register and memory array. f-we# is active low. addresses and data are latched on the rising edge of the second f-we# pulse. s-we# input sram write enable: controls writes to the sram memory array. s-we# is active low. s-ub# input sram upper byte enable: enables the upper byte for sram (dq 8 ?dq 15 ). s-ub# is active low. s-lb# input sram lower byte enable: enables the lower byte for sram (dq 0 ?dq 7 ). s-lb# is active low. f-rp# input flash reset/deep power-down: uses two voltage levels (v il , v ih ) to control reset/deep power-down mode. when f-rp# is at logic low, the device is in reset/deep power-down mode , which drives the outputs to high-z, resets the write state machine, and minimizes current levels (i ccd ). when f-rp# is at logic high, the device is in standard operation . when f-rp# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 10 datasheet f-wp# input flash write protect: controls the lock-down function of the flexible locking feature. when f-wp# is a logic low, the lock-down mechanism is enabled and blocks marked lock- down cannot be unlocked through software. when f-wp# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. after f-wp# goes low, any blocks previously marked lock-down revert to that state. see section 7.0, ?system design considerations? on page 41 for details on block locking. f-vcc supply flash power supply: [2.7 v?3.3 v] supplies power for device core operations. f-vccq supply flash i/o power supply: [2.7 v?3.3 v] supplies power for device i/o operations. s-vcc supply sram power supply: [2.7 v?3.3 v] supplies power for device operations. see section 7.2.2, ?f-vcc, f-vpp and f-rp# transition? on page 42 for details of power connections. f-vpp input / supply flash program/erase power supply: [1.65 v?3.3 v or 11.4 v?12.6 v] operates as an input at logic levels to control complete flash protection. supplies power for accelerated flash program and erase operations in 12 v 5% range. this ball cannot be left floating. lower f- v pp v pplk , to protect all contents against program and erase commands. set f-v pp =f-v cc for in-system read, program and erase operations. in this configuration, f-v pp can drop as low as 1.65 v to allow for resistor or diode drop from the system supply. note that if f-v pp is driven by a logic signal, v ih = 1.65 v. that is, f-v pp must remain above 1.65 v to perform in-system flash modifications. raise f-v pp to 12 v 5% for faster program and erase in a production environment. applying 12 v 5% to f-v pp can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. f-vss supply flash ground: for all internal circuitry. all ground inputs must be connected. s-vss supply sram ground: for all internal circuitry. all ground inputs must be connected. nc not connected: internally disconnected within the device. table 2. 3 volt intel ? advanced+ boot block stacked-csp ball descriptions (sheet 2 of 2) symbol type name and function 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 11 2.0 principles of operation the flash memory utilizes a cui and automated algorithms to simplify program and erase operations. the wsm automates program and erase operations by handling data and address latches, we#, and system status requests. . 2.1 bus operation all bus cycles to or from the stacked-csp conform to standard microcontroller bus cycles. four control signals dictate the data flow in and out of the flash component: f-ce#, f-oe#, f-we# and f-rp#. four separate control signals handle the data flow in and out of the sram component: s-cs1#, s-cs2, s-oe#, and s-we#. these bus operations are summarized in table 2 and table 3 . 2.1.1 read the flash memory has four read modes: read array, read identifier, read status and cfi query. these flash memory read modes are not dependent on the f-v pp voltage. upon initial device power - up or after exit from reset, the flash device automatically defaults to read array mode. f-ce# and f-oe# must be asserted to obtain data from the flash component. the sram has one read mode available. s-cs1#, s-cs2, and s-oe# must be asserted to obtain data from the sram device. see table 3, ?3 volt intel advanced+ boot block flash memory stacked-csp bus operations? on page 12 for a summary of operations. figure 2. 3 volt intel ? advanced+ boot block stacked chip scale package block diagram f-vcc f-oe# f-ce# a[max:0] 2-, 4- or 8-mbit sram 28f160c3 or 28f320c3 flash s-vcc f-vccq s-cs1 s-cs2 s-oe# s-we# s-ub# s-lb# f-vpp f-we# f-vss s-vss d[15:0] f-wp# f-rp# 3 volt intel ? advanced+ boot block flash memory stacked-csp family 12 datasheet 2.1.2 output disable with f-oe# and s-oe# deasserted, the stacked-csp outputs signals are placed in a high - impedance state. 2.1.3 standby with f-ce# and s-cs1# or s-cs2 deasserted, the stacked-csp enters a standby mode, which substantially reduces device power consumption. in standby, outputs are placed in a high- impedance state independent of f-oe# and s-oe#. if the flash is deselected during a program or erase operation, the flash continues to consume active power until the program or erase operation is complete. table 3. 3 volt intel advanced+ boot block flash memory stacked-csp bus operations modes flash signals sram signals memory output notes f-rp# f-ce# f-oe 1 # f-we# s-cs 1 # s-cs 2 s-oe 1 # s-we# s-ub#,s-lb# (1) memory bus control d 0 ? d 15 flash read h l l h sram must be in high z flash d out 2,3,4 write h l h l flash d in 2,4 standby h h x x any sram mode is allowable other high z5,6 output disable h l h h other high z5,6 reset l x x x other high z5,6 sram read flash must be in high z lhlhlsramd out 2,4 write l h h l l sram d in 2,4 standby any flash mode is allowable hxxxx other high z 4,5,6 xlxxx output disable l h h h x other high z 4,5,6 data retention same as a standby other high z 4,5,7 notes: 1. two devices may not drive the memory bus at the same time. 2. the sram may be placed into data retention mode by lowering the s-v cc to the v dr range, as specified. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 13 2.1.4 flash reset the device enters a reset mode when rp# is driven low. in reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. after return from reset, a time t phqv is required until outputs are valid, and a delay (t phwl or t phel ) is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. the device defaults to read array mode, the status register is set to 80h, and the read configuration register defaults to asynchronous reads. if rp# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. 2.1.5 write writes to flash take place when both f-ce# and f-we# are asserted and f-oe# is deasserted. writes to sram take place when both s-cs1# and s-we# are asserted and s-oe# and s-cs2 are deasserted. commands are written to the flash memory?s command user interface (cui) using standard microprocessor write timings to control flash operations. the cui does not occupy an addressable memory location within the flash component. the address and data buses are latched on the rising edge of the second f-we# or f-ce# pulse, whichever occurs first. (see figure 6 and figure 7 for read and write waveforms.) 3.0 flash memory modes of operation the flash memory has four read modes: read array, read configuration, read status, and cfi query. the write modes are program and erase. three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. these modes are reached using the commands summarized in table 5, ?flash memory command definitions? on page 17 . 3.1 read array (ffh) when f-rp# transitions from v il (reset) to v ih , the device defaults to read array mode and will respond to the read control inputs without any additional cui commands. in addition, the address of the desired location must be applied to the address balls. if the device is not in read array mode, as would be the case after a program or erase operation, the read array command (ffh) must be written to the cui before array reads can take place. 3.2 read identifier (90h) the read configuration mode outputs the manufacturer/device identifier. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in table 4, ?read configuration table? on page 14 retrieve the specified information. to return to read array mode, write the read array command (ffh). 3 volt intel ? advanced+ boot block flash memory stacked-csp family 14 datasheet the read configuration mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in table 4 retrieve the specified information. to return to read array mode, write the read array command (ffh). other locations within the configuration address space are reserved by intel for future use. 3.3 read status register (70h) the status register indicates the status of device operations, and the success/failure of that operation. the read status register (70h) command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the array, issue a read array (ffh) command. the status register bits are output on dq[7:0]. the upper byte, dq[15:8], outputs 00h during a read status register command. the contents of the status register are latched on the falling edge of f-oe# or f-ce#, whichever occurs last. this prevents possible bus errors which might occur if status register contents change while being read. f-ce# or f-oe# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the wsm is active, sr7 will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the desired operation (see table 6, ?flash memory status register definition? on page 18 ). 3.3.1 clear status register (50h) the wsm sets status bits 1 through 7 to ?1,? and clears bits 2, 6 and 7 to ?0,? but cannot clear status bits 1 or 3 through 5 to ?0.? because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the use of the clear status register (50h) command. by allowing the system software to control the resetting of these bits, several operations may be performed table 4. read configuration table item address data notes manufacturer code (x16) 0x00000 0x0089 device id (see appendix d) 0x00001 id block lock configuration 0xxx002 lock 1, 2 ? block is unlocked dq 0 =0 ? block is locked dq 0 =1 ? block is locked-down dq 1 =1 protection register lock 0x80 pr-lk 3 protection register (x16) 0x81-0x88 pr notes: 1. see section 3.7 for valid lock status outputs. 2. ?xx? specifies the block address of lock configuration being read. 3. see section 3.8 for protection register information. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 15 (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. clear the status register before beginning another command or sequence. note that the read array command must be issued before data can be read from the memory array. resetting the device also clears the status register. 3.4 cfi query (98h) the cfi query mode outputs common flash interface (cfi) data when the device is read. this can be accessed by writing the cfi query command (98h). the cfi data structure contains information such as block size, density, command set and electrical specifications. once in this mode, read cycles from addresses shown in appendix b retrieve the specified information. to return to read array mode, write the read array command (ffh). 3.5 word program (40h/10h) programming is executed using a two - write sequence. the program setup command (40h) is written to the cui followed by a second write which specifies the address and data to be programmed. the wsm will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. programming the memory results in specific bits within an address location being changed to a ?0.? if the user attempts to program ?1?s, the memory cell contents do not change and no error occurs. the status register indicates programming status: while the program sequence executes, status bit 7 is ?0.? the status register can be polled by toggling either f-ce# or f-oe#. while programming, the only valid commands are read status register, program suspend, and program resume. when programming is complete, the program status bits should be checked. if the programming operation was unsuccessful, bit sr.4 of the status register is set to indicate a program failure. if sr.3 is set then f-v pp was not within acceptable limits, and the wsm did not execute the program command. if sr.1 is set, a program operation was attempted on a locked block and the operation was aborted. the status register should be cleared before attempting the next operation. any cui instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the cui to read array mode. 3.5.1 suspending and resuming program (b0h/d0h) the program suspend command halts an in - progress program operation so that data can be read from other locations of memory. once the programming process starts, writing the program suspend command to the cui requests that the wsm suspend the program sequence (at predetermined points in the program algorithm). the device continues to output status register data after the program suspend command is written. polling status register bits sr.7 and sr.2 will determine when the program operation has been suspended (both will be set to ?1?). t whrh1 / t ehrh1 specify the program suspend latency. a read array command can be written to the cui to read data from any block other than the suspended block. the only other valid commands, while program is suspended, are read status register, read configuration, cfi query, and program resume. after the program resume 3 volt intel ? advanced+ boot block flash memory stacked-csp family 16 datasheet command is written to the flash memory, the wsm will continue with the programming process and status register bits sr.2 and sr.7 will automatically be cleared. the device automatically outputs status register data when read (see appendix a, program suspend/resume flowchart s) after the program resume command is written. f-v pp must remain at the same f-v pp level used for program while in program suspend mode. f-rp# must also remain at v ih . 3.6 block erase (20h) to erase a block, write the erase set - up and erase confirm commands to the cui, along with an address identifying the block to be erased. this address is latched internally when the erase confirm command is issued. block erasure results in all bits within the block being set to ?1.? only one block can be erased at a time. the wsm will execute a sequence of internally timed events to program all bits within the block to ?0,? erase all bits within the block to ?1,? then verify that all bits within the block are sufficiently erased. while the erase executes, status bit 7 is a ?0.? when the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. if the erase operation was unsuccessful, sr.5 of the status register will be set to a ?1,? indicating an erase failure. if f-v pp was not within acceptable limits after the erase confirm command was issued, the wsm will not execute the erase sequence; instead, sr.5 of the status register is set to indicate an erase error, and sr.3 is set to a ?1? to identify that f-v pp supply voltage was not within acceptable limits. after an erase operation, clear the status register (50h) before attempting the next operation. any cui instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete. 3.6.1 suspending and resuming erase (b0h/d0h) an erase operation can take several seconds to complete, therefore, the erase suspend command is provided to allow erase - sequence interruption in order to read data from, or program data to, another block in memory. once an erase sequence has started, writing the erase suspend command to the cui causes the device to suspend the erase sequence at a predetermined point in the erase algorithm. block erase is suspended when status register bits sr[7,6] are set. suspend latency is specified in section 5.7, ?flash erase and program timings? on page 31. when an erase operation has been suspended, a word program or read operation can be performed within any block, except the block that is in an erase suspend state. an erase operation cannot be nested within another erase suspend operation. a suspended erase operation cannot resume until the nested program operation has completed. read array, read status register, clear status register, read identifier, cfi query, erase resume, are all valid commands during erase suspend. additionally, program, program suspend, program resume, lock block, unlock block and lock-down block are valid commands during erase suspend. to resume an erase suspend operation, issue the resume command. the resume command can be written to any device address. when a program operation is nested within an erase suspend operation and the program suspend command is issued, the device will suspend the program operation. when the resume command is issued, the device will resume the program operation first. once the nested program operation is completed, an additional resume command is required to complete the block operation. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 17 table 5. flash memory command definitions command note first bus cycle second bus cycle operation address data operation address data read array 1 write x ffh read identifier 1, 2 write x 90h read ia id cfi query 1, 2 write x 98h read qa qd read status register 1 write x 70h read x srd clear status register 1 write x 50h word program 1, 3 write x 40h/10h write pa pd block erase/confirm 1 write x 20h write ba d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h lock block 1 write x 60h write ba 01h unlock block 1, 4write x 60hwrite ba d0h lock-down block 1 write x 60h write ba 2fh protection register program 1 write x c0h write pa pd lock protection register 1 write x c0h write pa fffd x = don?t care pa = program address ba = block address ia = identifier address qa = query address srd = status register data pd = program data id = identifier data qd = query data notes: 1. when writing commands, the upper data bus [dq 8 ?dq 15 ] should be either v il or v ih , to minimize current draw. 2. following the read configuration or cfi query commands, read operations output device configuration or cfi query information, respectively. 3. either 40h or 10h command is valid, but the intel standard is 40h. 4. when unlocking a block, wp# must be held for three clock cycles (1 clock cycle after the second command bus cycle). 3 volt intel ? advanced+ boot block flash memory stacked-csp family 18 datasheet 3.7 block locking the instant, individual block locking feature that allows any flash block to be locked or unlocked with no latency, which enables instant code and data protection. this locking offers two levels of protection. the first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). the following sections will discuss the operation of the locking system. the term ?state [xyz]? will be used to specify locking states; e.g., ?state [001],? where x=value of wp#, y = bit dq 1 of the block lock status register, and z = bit dq 0 of the block lock status register. table 8, ?block locking state transitions? on page 21 defines all of these possible locking states. table 6. flash memory status register definition wsms ess es ps vpps pss bls r 76543210 notes: sr.7 write state machine status 1 = ready (wsms) 0=busy check write state machine bit first to determine word program or block erase completion, before checking program or erase status bits. sr.6 = erase - suspend status (ess) 1=erase suspended 0=erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ?1.? ess bit remains set to ?1? until an erase resume command is issued. sr.5 = erase status (es) 1 = error in block erase 0 = successful block erase when this bit is set to ?1,? wsm has applied the max. number of erase pulses and is still unable to verify successful block erasure. sr.4 = program status (ps) 1 = error in programming 0 = successful programming when this bit is set to ?1,? wsm has attempted but failed to program a word/byte. sr.3 = f-v pp status (vpps) 1=f-v pp low detect, operation abort 0=f-v pp ok the f-v pp status bit does not provide continuous indication of v pp level. the wsm interrogates f-v pp level only after the program or erase command sequences have been entered, and informs the system if f-v pp has not been switched on. the f-v pp is also checked before the operation is verified by the wsm. the f-v pp status bit is not guaranteed to report accurate feedback between v pplk and v pp1 min. sr.2 = program suspend status (pss) 1=program suspended 0=program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to ?1.? pss bit remains set to ?1? until a program resume command is issued. sr.1 = block lock status 1=prog/erase attempted on a locked block; operation aborted. 0=no operation to locked blocks if a program or erase operation is attempted to one of the locked blocks, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr.0 = reserved for future enhancements (r) this bit is reserved for future use and should be masked out when polling the status register. note: a command sequence error is indicated when sr.4, sr.5 and sr.7 are set. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 19 3.7.1 block locking operation summary the following concisely summarizes the locking functionality. all blocks are locked when powered-up, and can be unlocked or locked with the unlock and lock commands. ? the lock-down command locks a block and prevents it from being unlocked when wp# = 0. ? when wp# = 1, lock-down is overridden and commands can unlock/lock locked-down blocks. ? when wp# returns to 0, locked-down blocks return to lock-down. ? lock-down is cleared only when the device is reset or powered-down. the locking status of each block can set to locked, unlocked, and lock-down, each of which will be described in the following sections. a comprehensive state table for the locking functions is shown in table 8 on page 21 , and a flowchart for locking operations is shown in figure 19 on page 50 . 3.7.2 locked state the default status of all blocks upon power-up or reset is locked (states [001] or [101]). locked blocks are fully protected from alteration. any program or erase operations attempted on a locked block will return an error on bit sr.1 of the status register. the status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. unlocked blocks can be locked issuing the ?lock? command sequence, 60h followed by 01h. 3.7.3 unlocked state unlocked blocks (states [000], [100], [110]) can be programmed or erased. all unlocked blocks return to the locked state when the device is reset or powered down. the status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. a locked block can be unlocked by writing the unlock command sequence, 60h followed by d0h. 3.7.4 lock-down state blocks that are locked-down (state [011]) are protected from program and erase operations (just like locked blocks), but their protection status cannot be changed using software commands alone. a locked or unlocked block can be locked-down by writing the lock-down command sequence, 60h followed by 2fh. locked-down blocks revert to the locked state when the device is reset or powered down. the lock-down function is dependent on the wp# input ball. when wp# = 0, blocks in lock- down [011] are protected from program, erase, and lock status changes. when wp# = 1, the lock- down function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. these blocks can then be re-locked [111] and unlocked [110] as desired while wp# remains high. when wp# goes low, blocks that were previously locked-down return to the lock-down state [011] regardless of any changes made while wp# was high. device reset or power-down resets all blocks, including those in lock-down, to locked state. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 20 datasheet 3.7.5 reading a block?s lock status the lock status of every block can be read in the configuration read mode of the device. to enter this mode, write 90h to the device. subsequent reads at block address + 00002 will output the lock status of that block. the lock status is represented by the least significant outputs, dq 0 and dq 1 . dq 0 indicates the block lock/unlock status and is set by the lock command and cleared by the unlock command. it is also automatically set when entering lock-down. dq 1 indicates lock- down status and is set by the lock-down command. it cannot be cleared by software, only by device reset or power-down. 3.7.6 locking operation during erase suspend changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. this is useful in the case when another block needs to be updated while an erase operation is in progress. to change block locking during an erase operation, first write the erase suspend command (b0h), then check the status register until it indicates that the erase operation has been suspended. next write the desired lock command sequence to a block and the lock status will be changed. after completing any desired lock, read, or program operations, resume the erase operation with the erase resume command (d0h). if a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. locking operations cannot be performed during a program suspend. 3.7.7 status register error checking using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. since locking changes are performed using a two cycle command sequence, e.g., 60h followed by 01h to lock a block, following the configuration setup command (60h) with an invalid command will produce a lock command error (sr.4 and sr.5 will be set to 1) in the status register. if a lock command error occurs during an erase suspend, sr.4 and sr.5 will be set to 1, and will remain at 1 after the erase is resumed. when erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. a similar situation happens if an error occurs during a program operation error nested within an erase suspend. table 7. block lock status item address data block lock configuration xx002 lock ? block is unlocked dq 0 =0 ? block is locked dq 0 =1 ? block is locked-down dq 1 =1 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 21 3.8 128 bit protection register the 3 volt intel ? advanced+ stacked-csp architecture includes a 128-bit protection register than can be used to increase the security of a system design. for example, the number contained in the protection register can be used to ?mate? the flash component with other system components such as the cpu or asic, preventing device substitution. 3.8.1 reading the protection register the protection register is read in the configuration read mode. the device is switched to this mode by writing the read configuration command (90h). once in this mode, read cycles from addresses shown in appendix e retrieve the specified information. to return to read array mode, write the read array command (ffh). 3.8.2 programming the protection register (c0h) the protection register bits are programmed using the two-cycle protection program command. the 64-bit number is programmed 16 bits at a time for word-wide parts. first write the protection program setup command, c0h. the next write to the device will latch in address and data and program the specified location. the allowable addresses are shown in appendix e. see figure 20, ?protection register programming flowchart? on page 51 . table 8. block locking state transitions current state erase/ program allowed? next state after command input wp# dq 1 dq 0 name lock unlock lock-down 0 0 0 unlocked yes go to [001] ? go to [011] 1 0 0 unlocked yes go to [101] ? go to [111] 0 0 1 locked (default) no ? go to [000] go to [011] 1 0 1 locked no ? go to [100] go to [111] 0 1 1 locked-down no ? ? ? 110 lock-down disabled ye s g o to [111] ? go to [111] 111 no - go to [110] ? notes: 1. ??? indicates no change in the current state. 2. in this table, the notation [xyz] denotes the locking state of a block, where x=wp#, y=dq 1 , and z=dq 0 . the current locking state of a block is defined by the state of wp# and the two bits of the block lock status (dq 0 , dq 1 ). dq 0 indicates if a block is locked (1) or unlocked (0). dq 1 indicates if a block has been locked-down (1) or not (0). 3. at power-up or device reset, all blocks default to locked state [001] (if wp# = 0). holding wp# = 0 is the recommended default. 4. the ?erase/program allowed?? column shows whether erase and program operations are enabled (yes) or disabled (no) in that block?s current locking state. 5. the ?lock command input result [next state]? column shows the result of writing the three locking commands (lock, unlock, lock-down) in the current locking state. for example, ?goes to [001]? would mean that writing the command to a block in the current locking state would change it to [001]. 6. the 128 bits of the protection register are divided into two 64-bit segments. one of the segments is programmed at the intel factory with a unique 64 bit number, which is unchangeable. the other segment is left blank for customer designs to program as desired. once the customer segment is programmed, it can be locked to prevent reprogramming. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 22 datasheet any attempt to address protection program commands outside the defined protection register address space will result in a status register error (program error bit sr.4 will be set to 1). attempting to program or to a previously locked protection register segment will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). 3.8.3 locking the protection register the user-programmable segment of the protection register is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the intel factory to protect the unique device number. this bit is set using the protection program command to program fffdh to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. a protection program command to locked words will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). the protection register lockout state is not reversible. 0645_05 figure 3. protection register memory map 4 words factory programmed 4 words user programmed pr-lock 88h 85h 84h 81h 80h 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 23 4.0 power and reset considerations 4.1 power-up/down characteristics in order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up f-v cc , f-v ccq and s-v cc together. conversely, f-v cc , f-v ccq and s-v cc must power-down together. it is also recommended to power-up f-v pp with or slightly after f-v cc . conversely, f-v pp must power down with or slightly before f-v cc . if f-v ccq and/or f-v pp are not connected to the f-v cc supply, then f-v cc should attain f- v cc min before applying f-v ccq and f-v pp . device inputs should not be driven before supply voltage = f-v cc min. power supply transitions should only occur when f-rp# is low. 4.2 additional flash features intel 3 volt advanced+ stacked-csp products provide in-system programming and erase in the 1.65 v?3.3 v range. for fast production programming, it also includes a low-cost, backward- compatible 12 v programming feature. 4.2.1 improved 12 volt production programming when f-v pp is between 1.65 v and 3.3 v, all program and erase current is drawn through the f-v cc signal. note that if f-v pp is driven by a logic signal, v ih min = 1.65 v. that is, f-v pp must remain above 1.65 v to perform in-system flash modifications. when f-v pp is connected to a 12 v power supply, the device draws program and erase current directly from the f-v pp signal. this eliminates the need for an external switching transistor to control the voltage f-v pp . figure 12, ?example power supply configurations? on page 42 shows examples of how the flash power supplies can be configured for various usage models. the 12 v f-v pp mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 v may be applied to f-v pp during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. stressing the device beyond these limits may cause permanent damage. 4.2.2 f-v pp v pplk for complete protection in addition to the flexible block locking, the f-v pp programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. when f-v pp is below v pplk , any program or erase operation will result in a error, prompting the corresponding status register bit (sr.3) to be set. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 24 datasheet 5.0 electrical specifications 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. notice: this datasheet contains information on products in full production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 9. absolute maximum ratings parameter maximum rating notes extended operating temperature ?25c to +85c during read during flash block erase and program temperature under bias storage temperature ?65c to +125c voltage on any ball (except f-vcc /f-vccq / s-vcc and f-vpp) with respect to gnd ?0.5 v to +3.3 v 1 f-v pp voltage (for block erase and program) with respect to gnd ?0.5 v to +13.5 v 1,2,4 f-v cc / f-v ccq / s-v cc supply voltage with respect to gnd ?0.2v to +3.3 v output short circuit current 100 ma 3 notes: 1. minimum dc voltage is ?0.5 v on input/output balls. during transitions, this level may undershoot to ? 2.0 v for periods < 20 ns. maximum dc voltage on input/output balls is f-v cc / f-v ccq / s-v cc + 0.5 v which, during transitions, may overshoot to f-v cc / f-v ccq / s-v cc + 2.0 v for periods < 20 ns. 2. maximum dc voltage on f-v pp may overshoot to +14.0 v for periods < 20 ns. 3. f-v pp voltage is normally 1.65 v?3.3 v. connection to supply of 11.4 v?12.6 v can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. f-v pp may be connected to 12 v for a total of 80 hours maximum. see section 4.2.1 for details 4. output shorted for no more than one second. no more than one output shorted at a time. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 25 5.2 operating conditions 5.3 capacitance t case = +25c, f = 1 mhz table 10. temperature and voltage operating conditions symbol parameter notes min max units t case operating temperature ?25 +85 c v cc / v ccq f-v cc /f-v ccq /s-v cc supply voltage 12.73.3volts v pp1 supply voltage 1 1.65 3.3 volts v pp2 1, 2 11.4 12.6 volts cycling block erase cycling 2 100,000 cycles notes: 1. f-v cc /f-v ccq must share the same supply. f-v cc /s-v cc must share the same supply when not in data retention. 2. applying f-v pp = 11.4 v?12.6 v during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. see section 4.2.1 for details. sym parameter notes typ max units conditions c in input capacitance 1 16 18 pf v in =0v c out output capacitance 1 20 22 pf v out =0v note: sampled, not 100% tested. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 26 datasheet 5.4 dc characteristics table 11. dc characteristics (sheet 1 of 2) symbol parameter device note 2.7 v ? 3.3 v unit test conditions typ max i li input load current flash/ sram 1 2a f-v cc /s-v cc =v cc max v in =v cc max or gnd i lo output leakage current flash/ sram 10.2 10 a f-v cc /s-v cc =v cc max v in =v cc max or gnd i ccs v cc standby current 0.25m flash 11025 a f-v cc =v cc max f-ce# = f-rp# = v cc f-wp# = v cc or gnd v in =v cc max or gnd 0.13m and 0.18m flash 1715 2-mb sram 1-10a s-v cc =v cc max s-cs1# = v cc , s-cs2 = v cc or s-cs2 = gnd v in =v cc max or gnd 4-mb sram 1-15a 8-mb sram 1-25a i ccd v cc deep power-down current 0.25m flash 1725 a f-v cc =v cc max v in =v cc max or gnd f-rp# = gnd 0.2 v 0.13m and 0.18m flash 1715 i cc operating power supply current (cycle time = 1 s) 2-mb sram 1-7ma i io =0 ma, s-cs1# = v il s-cs2 = s-we# =v ih v in =v il or v ih 4-mb sram 1-10ma 8-mb sram 1-10ma i cc2 operating power supply current (min cycle time) 2-mb sram 1-40ma cycle time = min, 100% duty, i io =0 ma, s-cs1# = v il , s-cs2 = v ih, v in =v il or v ih 4-mb sram 1-45ma 8-mb sram 1-50ma i ccr v cc read current 0.25m flash 1,2 10 18 ma f-v cc =v cc max f-oe# = v ih , f-ce# = v il f=5 mhz, i out =0 ma v in =v il or v ih 0.13m and 0.18m flash 1,2 9 18 ma 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 27 i ccw v cc program current flash 1,3 18 55 ma f-v pp =v pp1 program in progress 822ma f-v pp =v pp2 (12 v) program in progress i cce v cc erase current flash 1,3 16 45 ma f-v pp =v pp1 erase in progress 815ma f-v pp =v pp2 (12 v) erase in progress i cces v cc erase suspend current flash 1,3,4 7 15 a f-ce# = v cc , erase suspend in progress i ccws v cc program suspend current 0.25 m flash 1,3,4 10 25 a f-ce# = v cc , program suspend in progress 0.13m and 0.18m flash 1,3,4 7 15 i ppd f-v pp deep power-down current flash 1 0.2 5 a f-rp# = gnd 0.2 v f-v pp v cc i pps f-v pp standby current flash 1 0.2 5 a f-v pp v cc i ppr f-v pp read current flash 12 15 a f-v pp v cc 1,2 50 200 a f-v pp v cc i ppw f-v pp program current flash 1,2 0.05 0.1 ma f-v pp =v pp1 program in progress 822ma f-v pp =v pp2 (12 v) program in progress i ppe f-v pp erase current flash 1,2 0.05 0.1 ma f-v pp =v pp1 erase in progress i ppes f-v pp erase suspend current flash 1,2 0.2 5 a f-v pp =v pp1 erase suspend in progress 50 200 a f-v pp =v pp2 (12 v) erase suspend in progress i ppws f-v pp program suspend current flash 1,2 0.2 5 a f-v pp =v pp1 program suspend in progress 50 200 a f-v pp =v pp2 (12 v) program suspend in progress notes: 1. all currents are in rms unless otherwise noted. typical values at nominal f-v cc /s-v cc , t case =+25 c. 2. automatic power savings (aps) reduces i ccr to approximately standby levels in static operation (cmos inputs). 3. sampled, not 100% tested. 4. i cces and i ccws are specified with device de-selected. if device is read while in erase suspend, current draw is sum of i cces and i ccr . if the device is read while in program suspend, current draw is the sum of i ccws and i ccr . table 11. dc characteristics (sheet 2 of 2) symbol parameter device note 2.7 v ? 3.3 v unit test conditions typ max 3 volt intel ? advanced+ boot block flash memory stacked-csp family 28 datasheet 0645_07 0666_05 note: c l includes jig capacitance. table 12. dc characteristics symbol parameter device note 2.7 v ? 3.3 v units test conditions min max v il input low voltage flash/ sram ?0.2 0.6 v v ih input high voltage flash/ sram 2.3 v cc +0.2 v v ol output low voltage flash/ sram ?0.10 0.10 v f-v cc /s-v cc =v cc min i ol =100 a v oh output high voltage flash/ sram v cc ? 0.1 v f-v cc /s-v cc =v cc min i oh = ?100 a v pplk f-v pp lock-out voltage flash 1 1.0 v complete write protection v pp1 f-v pp during program / erase flash 1 1.65 3.3 v v pp2 operations 1,2 11.4 12.6 v lko v cc prog/erase lock voltage flash 1.5 v v lko2 v ccq prog/erase lock voltage flash 1.2 v notes: 1. erase and program are inhibited when f-v pp < v pplk and not guaranteed outside the valid f-v pp ranges of v pp1 and v pp2 . 2. applying f-v pp = 11.4v?12.6v during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. f-v pp may be connected to 12 v for a total of 80 hours maximum. see section 4.2.1 for details. figure 4. input/output reference waveform note: ac test inputs are driven at v ccq for a logic ?1? and 0.0v for a logic ?0.? input timing begins, and output timing ends, at v ccq /2. input rise and fall times (10%?90%) <10 ns. worst case speed conditions are when v ccq = v ccq min. input output test points v cc 0.0 v cc 2 v cc 2 figure 5. test configuration device under test out c l 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 29 5.5 flash ac characteristics. flash test configuration component values table test configuration c l (pf) 2.7 v?3.3 v standard tes t 5 0 table 13. flash ac characteristics?read operations # sym parameter density 16-mbit 32-mbit unit product -70 -90 -110 -70 -90 voltage range 2.7 v - 3.3 v note min max min max min max min max min max r1 t avav read cycle time 70 90 110 70 90 ns r2 t avqv address to output delay 70 90 110 70 90 ns r3 t elqv f-ce# to output delay 1 70 90 110 70 90 ns r4 t glqv f-oe# to output delay 1 20 30 30 20 20 ns r5 t phqv f-rp# to output delay 150 150 150 150 150 ns r6 t elqx f-ce# to output in low z 2000 0 0ns r7 t glqx f-oe# to output in low z 2000 0 0ns r8 t ehqz f-ce# to output in high z 2 20 25 25 20 20 ns r9 t ghqz f-oe# to output in high z 2 20 20 20 20 20 ns r10 t oh output hold from address f-ce#, or f-oe# change, whichever occurs first 2000 0 0ns notes: 1. f-oe# may be delayed up to t elqv ?t glqv after the falling edge of ce# without impact on t elqv 2. sampled, but not 100% tested. 3. see figure 6, ?ac waveform: flash read operations? on page 30 . 4. see figure 4, ?input/output reference waveform? on page 28 for timing measurements and maximum allowable input slew rate. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 30 datasheet figure 6. ac waveform: flash read operations a ddress stable device and a ddress selection ih v il v a ddresses ( a ) ih v il v ih v il v ih v il v ce# (e) oe# (g) we# (w) d a t a (d/q) ih v il v rp#(p) ol v oh v high z valid output data valid standby high z r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 31 5.6 flash ac characteristics?write operations see figure 4, ?input/output reference waveform? on page 28 for timing measurements and maximum allowable input slew rate. see figure 7, ?ac waveform: flash program and erase operations? on page 33 . 5.7 flash erase and program timings (1) table 14. flash ac characteristics?write operations # sym parameter density 16-mbit 32-mbit unit product -70 -90 -110 -70 -90 voltage range 2.7 v - 3.3 v note min min min min min w1 t phwl t phel f-rp# high recovery to f-we# (f-ce#) going low 150 150 150 150 150 ns w2 t elwl t wlel f-ce# (f-we#) setup to f-we# (f-ce#) going low 0 0 0 0 0 ns w3 t eleh t wlwh f-we# (f-ce#) pulse width 1 45 60 70 45 60 ns w4 t dvwh t dveh data setup to f-we# (f-ce#) going high 2 40 50 60 40 40 ns w5 t avwh t aveh address setup to f-we# (f-ce#) going high 2 50 60 70 50 60 ns w6 t wheh t ehwh f-ce# (f-we#) hold time from f-we# (f-ce#) high 0 0 0 0 0 ns w7 t whdx t ehdx data hold time from f-we# (f-ce#) high 2 0 0 0 0 0 ns w8 t whax t ehax address hold time from f-we# (f-ce#) high 2 0 0 0 0 0 ns w9 t whwl t ehel f-we# (f-ce#) pulse width high 1 25 30 30 25 30 ns w10 t vpwh t vpeh f-v pp setup to f-we# (f-ce#) going high 3 200 200 200 200 200 ns w11 t qvvl f-v pp hold from valid srd 3 00000ns notes: 1. write pulse width (t wp ) is defined from f-ce# or f-we# going low (whichever goes low last) to f-ce# or f-we# going high (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . similarly, write pulse width high (t wph ) is defined from f-ce# or f-we# going high (whichever goes high first) to f-ce# or f-we# going low (whichever goes low first). hence, t wph =t whwl =t ehel =t whel =t ehwl. 2. refer to tab l e 5, ?flash memory command definitions? on page 17 for valid a in or d in . 3. sampled, but not 100% tested. table 15. flash erase and program timings (sheet 1 of 2) symbol parameter f-v pp 1.65 v? 3.3 v 11.4 v? 12.6 v unit note typ (1) max typ (1) max t bwpb 4-kw parameter block program time (word) 2, 3 0.100.300.030.12 s t bwmb 32-kw main block program time (word) 2, 3 0.8 2.4 0.24 1 s t whqv1 / t ehqv1 0.25 m word program time 2, 322200 8 185 s 0.13 m and 0.18 m word program time 2, 312200 8 185 t whqv2 / t ehqv2 4-kw parameter block erase time (word) 2, 30.540.44 s 3 volt intel ? advanced+ boot block flash memory stacked-csp family 32 datasheet t whqv3 / t ehqv3 32-kw main block erase time (word) 2, 31 5 0.6 5 s t whrh1 / t ehrh1 program suspend latency 3 5 10 5 10 s t whrh2 / t ehrh2 erase suspend latency 3 5 20 5 20 s notes: 1. typical values measured at t case =+25 c and nominal voltages. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. table 15. flash erase and program timings (sheet 2 of 2) symbol parameter f-v pp 1.65 v? 3.3 v 11.4 v? 12.6 v unit note typ (1) max typ (1) max 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 33 notes: 1. f-ce# must be toggled low when reading status register data. f-we# must be inactive (high) when reading status register data. a. f-vcc power-up and standby. b. write program or erase setup command. c. write valid address and data (for program) or erase confirm command. d. automated program or erase delay. e. read status register data (srd): reflects completed program/erase operation. f. wr i te read array command. figure 7. ac waveform: flash program and erase operations addresses [a] ce#(we#) [e(w)] oe# [g] we#(ce#) [w(e)] data [d/q] rp# [p] ih v il v ih v il v ih v il v ih v il v il v il v in d in a in a valid srd in d ih v high z ih v il v v [v] pp pph v pplk v pph v1 2 wp# il v ih v in d ab c d e f w8 w6 w9 w3 w4 w7 w1 w5 w2 w10 w11 (note 1) (note 1) addresses [a] ce#(we#) [e(w)] oe# [g] we#(ce#) [w(e)] data [d/q] rp# [p] ih v il v ih v il v ih v il v ih v il v il v il v in d in a in a valid srd in d ih v high z ih v il v v [v] pp pph v pplk v pph v1 2 wp# il v ih v in d ab c d e f w8 w6 w9 w3 w4 w7 w1 w5 w2 w10 w11 (note 1) (note 1) 3 volt intel ? advanced+ boot block flash memory stacked-csp family 34 datasheet 5.8 flash reset operations figure 8. ac waveform: reset operation table 16. reset specifications (1) symbol parameter note f-v cc 2.7 v ? 3.3 v unit min max t plph f-rp# low to reset during read (if f-rp# is tied to v cc , this specification is not applicable) 2,4 100 ns t plrh1 f-rp# low to reset during block erase 3,4 22 s t plrh2 f-rp# low to reset during program 3,4 12 s notes: 1. see section 2.1.4, ?flash reset? on page 13 for a full description of these conditions. 2. if t plph is < 100 ns the device may still reset but this is not guaranteed. 3. if f-rp# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. sampled, but not 100% tested. ih v il v rp# (p) plph t ih v il v rp# (p) plph t (a) reset during read mode abort complete phqv t phwl t phel t phqv t phwl t phel t (b) reset during program or block erase, < plph t plr h t plrh t ih v il v rp# (p) plph t abort complete phqv t phwl t phel t plrh t deep power- down (c) reset program or block erase, > plph t plrh t 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 35 5.9 sram ac characteristics?read operations table 17. sram ac characteristics?read operations (1) #sym parameter density 2/4/8-mbit unit voltage range 2.7 v? 3.3 v note min max r1 t rc read cycle time 70 ? ns r2 t aa address to output delay ? 70 ns r3 t co1, t co2 s-cs1#, s-cs2 to output delay ? 70 ns r4 t oe s-oe# to output delay ? 35 ns r5 t ba s-ub#, lb# to output delay ? 70 ns r6 t lz1 , t lz2 s-cs1#, s-cs2 to output in low z2,35?ns r7 t olz s-oe# to output in low z30?ns r8 t hz1 , t hz2 s-cs1#, s-cs2 to output in high z 2,3,4 0 25 ns r9 t ohz s-oe# to output in high z3,4025ns r10 t oh output hold from address, s-cs1#, s-cs2, or s-oe# change, whichever occurs first 0?ns r11 t blz s-ub#, s-lb# to output in low z30?ns r12 t bhz s-ub#, s-lb# to output in high z3025ns note: 1. see figure 9, ?ac waveform: sram read operations? on page 36 . 2. at any given temperature and voltage condition, t hz (max) is less than and t lz (max) both for a given device and from device to device interconnection. 3. sampled, but not 100% tested. 4. timings of t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 36 datasheet figure 9. ac waveform: sram read operations high z valid output address stable data valid device address selection standby addresses (a) v ih v il v ih v il cs 1 # (e 1 ) v ih v il v oh v ol v ih oe# (g) we# (w) data (d/q) ub#, lb# high z v ih v il r1 r2 r4 r3 r6 r7 r8 r9 r10 cs 2 (e 2 ) v ih v il v ih r5 r11 r12 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 37 5.10 sram ac characteristics?write operations table 18. sram ac characteristics?write operations (1,2) #sym parameter density 2/4/8-mbit unit volt 2.7 v ? 3.3 v note min max w1 t wc write cycle time 70 ? ns w2 t as address setup to s-we# (s-cs1#) and s-ub#, s-lb# going low 30? ns w3 t wp s-we# (s-cs1#) pulse width 4 55 ? ns w4 t dw data to write time overlap 30 ? ns w5 t aw address setup to s-we# (s-cs1#) going high 60 ? ns w6 t cw s-ce# (s-we#) setup to s-we# (s-cs1#) going high 60 ? ns w7 t dh data hold time from s-we# (s-cs1#) high 0 ? ns w8 t wr write recovery 5 0 ? ns w9 t bw s-ub#, s-lb# setup to s-we# (s-cs1#) going high 60 ? ns notes: 1. see figure 10, ?ac waveform: sram write operations? on page 38 . 2. a write occurs during the overlap (t wp ) of low s-cs1# and low s-we#. a write begins when s-cs1# goes low and s-we# goes low with asserting s-ub# or s-lb# for single byte operation or simultaneously asserting s-ub# and s-lb# for double byte operation. a write ends at the earliest transition when s-cs1# goes high and s-we# goes high. the t wp is measured from the beginning of write to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wp is measured from s-cs1# going low to end of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as s-cs1# or s-we# going high. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 38 datasheet figure 10. ac waveform: sram write operations high z data in address stable device address selection standby addresses (a) v ih v il v ih v il cs 1 # (e 1 ) v ih v il v oh v ol v ih oe# (g) we# (w) data (d/q) ub#, lb# high z v ih v il w1 w8 cs 2 (e 2 ) v ih v il v ih w9 w6 w5 w2 w3 w4 w7 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 39 5.11 sram data retention characteristics ? extended temperature table 19. sram data retention characteristics (1) ?extended temperature sym parameter note min typ max unit test conditions v dr s-v cc for data retention 2 1.5 ? 3.3 v cs 1 # v cc ? 0.2 v i dr deep retention current - 8-mbit ??6a s-v cc =1.5v cs 1 # v cc ? 0.2 v deep retention current - 4-mbit ??5a deep retention current - 2-mbit ??4a t sdr data retention set-up time 0 ? ? ns see data retention waveform t rdr recovery time t rc ??ns notes: 1. typical values at nominal s-v cc , t case =+25 c. 2. s-cs1# v cc ? 0.2 v, s-cs2 v cc ? 0.2 v (s-cs1# controlled) or s-cs2 0.2 v (s-cs2 controlled). figure 11. sram data retention waveform v cc 3.0/2.7v cs 1 # (e 1 ) 2.2v v dr cs 2 (e 2 ) gnd v cc 3.0/2.7v 0.4v v dr gnd cs 1 # controlled cs 2 controlled data retention mode t sdr t rdr data retention mode t sdr t rdr 3 volt intel ? advanced+ boot block flash memory stacked-csp family 40 datasheet 6.0 migration guide information typically, it is important to discuss footprint migration compatibility between a new product and existing products. in this specific case, the stacked-csp allows the system designer to remove two separate memory footprints for individual flash and sram and replace them with a single footprint, thus resulting in an overall reduction in board space required. this implies that a new printed circuit board would be used to take advantage of this feature. since the flash in stacked-csp shares the same features as the advanced+ boot block features, conversions from the advanced boot block are described in ap-658 designing for upgrade to the advanced+ boot block flash memory, order number 292216 . please contact your local intel representation for detailed information about specific flash + sram system migrations. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 41 7.0 system design considerations this section contains information that would have been contained in a product design guide in earlier generations. in an effort to simplify the amount of documentation, relevant system design considerations have been combined into this document. 7.1 background the intel advanced+ boot block stacked chip scale package combines the features of the advanced+ boot block flash memory architecture with a low-power sram to achieve an overall reduction in system board space. this enables applications to integrate security with simple software and hardware configurations, while also combining the system sram and flash into one common footprint. this section discusses how to take full advantage of the 3 volt advanced+ boot block stacked chip scale package. 7.1.1 flash + sram footprint integration the stacked chip scale package memory solution can be used to replace a subset of the memory subsystem within a design. where a previous design may have used two separate footprints for sram and flash, you can now replace with the industry-standard i-ballout of the stacked-csp device. this allows for an overall reduction in board space, which allows the design to integrate both the flash and the sram into one component. 7.1.2 advanced+ boot block flash memory features advanced+ boot block adds the following new features to intel advanced boot block architecture: ? instant, individual block locking provides software/hardware controlled, independent locking/ unlocking of any block with zero latency to protect code and data. ? a 128-bit protection register enables system security implementations. ? improved 12 v production programming simplifies the system configuration required to implement 12 v fast programming. ? common flash interface (cfi) provides component information on the chip to allow software- independent device upgrades. for more information on specific advantages of the advanced+ boot block flash memory, please see ap-658 designing with the advanced+ boot block flash memory architecture . 7.2 flash control considerations the flash device is protected against accidental block erasure or programming during power transitions. power supply sequencing is not required, since the device is indifferent as to which power supply, f-vpp or f-vcc, powers-up first. example flash power supply configurations are shown in figure 12, ?example power supply configurations? on page 42 . 3 volt intel ? advanced+ boot block flash memory stacked-csp family 42 datasheet 7.2.1 f-rp# connected to system reset the use of f-rp# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. if a cpu reset occurs without a flash memory reset, proper cpu initialization will not occur because the flash memory may be providing status information instead of array data. intel recommends connecting f-rp# to the system cpu reset# signal to allow proper cpu/flash initialization following system reset. system designers must guard against spurious writes when f-v cc voltages are above v lko . since both f-we# and f-ce# must be low for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. the device is also disabled until f-rp# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset (f-rp# connected to system powergood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 7.2.2 f-v cc , f-v pp and f-rp# transition the cui latches commands as issued by system software and is not altered by f-v pp or f-ce# transitions or wsm actions. its default state upon power-up, after exit from reset mode or after f-v cc transitions above v lko (lockout voltage), is read array mode. after any program or block erase operation is complete (even after f-v pp transitions down to v pplk ), the cui must be reset to read array mode via the read array command if access to the flash memory array is desired. note: 1. a resistor can be used if the f-v cc supply can sink adequate current based on resistor value. figure 12. example power supply configurations v cc v pp 12 v fast programming absolute write protection with v pp v pplk system supply 12 v supply 10 k ? v cc v pp system supply 12 v supply low voltage and 12 v fast programming v cc v pp system supply prot# (logic signal) v cc v pp system supply low-voltage programming low-voltage programming absolute write protection via logic signal (note 1) 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 43 7.3 noise reduction stacked-csp memory?s power switching characteristics require careful device decoupling. system designers should consider three supply current issues for both the flash and sram: 1. standby current levels (i ccs ) 2. read current levels (i ccr ) 3. transient peaks produced by falling and rising edges of f-ce#, s-cs1#, and s-cs2. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two- line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each device should have a capacitors between individual power (f-vcc, f-vccq , f-vpp , s-vcc) and ground (gnd) signals. high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. noise issues within a system can cause devices to operate erratically if it is not adequately filtered. in order to avoid any noise interaction issues within a system, it is recommended that the design contain the appropriate number of decoupling capacitors in the system. noise issues can also be reduced if leads to the device are kept very short, in order to reduce inductance. decoupling capacitors between v cc and v ss reduce voltage spikes by supplying the extra current needed during switching. placing these capacitors as close to the device as possible reduces line inductance. the capacitors should be low inductance capacitors; surface mount capacitors typically exhibit lower inductance. it is highly recommended that systems use a 0.1 f capacitor for each of the d9, d10, a10 and e4 grid ballout locations (see figure 1, ?66-ball stacked chip scale package? on page 8 for ballout). these capacitors are necessary to avoid undesired conditions created by excess noise. smaller capacitors can be used to decouple higher frequencies. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 44 datasheet notes: 1. substrate connections refer to ballout locations shown in figure 1, ?66-ball stacked chip scale package? on page 8 . 2. 0.1 f capacitors should be used with d9, d10, a10and e4. 3. some sram devices do not have a s-vssq; in this case, this pad is a s-vss. 4. some sram devices do not have a s-vssq; in this case, this pad is a vcc. 7.4 simultaneous operation the term simultaneous operation in used to describe the ability to read or write to the sram while also programming or erasing flash. in addition, f-ce#, s-cs1# and s-cs2 should not be enabled at the same time. (see table 2, ?3 volt intel? advanced+ boot block stacked-csp ball descriptions? on page 9 for a summary of recommended operating modes.) simultaneous operation of the can be summarized by the following: ? sram read/write are during a flash program or erase operation are allowed. ? simultaneous bus operations between the flash and sram are not allowed (because of bus contention). figure 13. typical flash + sram substrate power and ground connections s-v ssq d10 sram die flash die substrate xx s-x f-x substrate connection to package ball sram die bond pad connection flash die bond pad connection s-v ccq s-v cc s-v ss f-v pp f-v ssq f-v cc f-v ccq f-v ss h8 a9 d9 e4 d3 a10 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 45 7.4.1 sram operation during flash ?busy? this functionality provides the ability to use both the flash and the sram ?at the same time? within a system, similar to the operation of two devices with separate footprints. this operation can be achieved by following the appropriate timing constraints within a system. 7.4.2 simultaneous bus operations operations that require both the sram and flash to be in active mode are disallowed. an example of these cases would include simultaneous reads on both the flash and sram, which would result in contention for the data bus. finally, a read of one device while attempting to write to the other (similar to the conditions of direct memory access (dma) operation) are also not within the recommended operating conditions. basically, only one memory can drive the outputs out the device at one given point in time. 7.5 printed circuit board notes the intel stacked-csp will save significant space on your pcb by combining two chips into one bga style package. intel stacked-csp has a 0.8 mm pitch that can be routed on your printed circuit board with conventional design rules. trace widths of 0.127 mm (0.005 inches) are typical. unused balls in the center of the package are not populated to further increase the routing options. standard surface mount process and equipment can be used for the intel stacked-csp. note: top view 7.6 system design notes summary the advanced+ boot block stacked-csp allows higher levels of memory component integration. different power supply configurations can be used within the system to achieve different objectives. at least three different 0.1 f capacitors should be used to decouple the devices within a system. sram reads or writes during a flash program or erase are supported operations. standard printed circuit board technology can be used. figure 14. standard pcb design rules can be used with stacked-csp device land pad diameter: 0.35 mm (0.0138 in) solder mask opening: 0.50 mm (0.0198 in) trace width: 0.127 mm (0.005 in) trace spaces: 0.160 mm (0.00625 in) via capture pad: 0.51 mm (0.020 in) via drill size: 0.25 mm (0.010 in) 3 volt intel ? advanced+ boot block flash memory stacked-csp family 46 datasheet appendix a program/erase flowcharts figure 15. automated word programming flowchart start write 40h program address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error programming error attempted program to locked block - aborted program successful sr.3 = sr.4 = sr.1 = full status check procedure bus operation write write standby repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases where multiple bytes are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1 0 1 0 1 0 command program setup program comments data = 40h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.1 1 = attempted program to locked block - program aborted read status register data toggle ce# or oe# to update status register data standby check sr.4 1 = v pp program error 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 47 0645_13 figure 16. program suspend/resume flowchart start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.2 = 1 write ffh read array data program completed done reading yes write ffh write d0h program resumed read array data 0 1 read array data from block other than the one being programmed. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.2 1 = program suspended 0 = program completed data = d0h addr = x bus operation command 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write write read read standby standby write data = 70h addr = x command program suspend read status read array program resume 3 volt intel ? advanced+ boot block flash memory stacked-csp family 48 datasheet 0645_14 figure 17. automated block erase flowchart start write 20h write d0h and block address read status register sr.7 = full status check if desired block erase complete full status check procedure bus operation write write standby repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last write operation to reset device to read array mode. bus operation standby sr. 1 and 3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. sr.1, 3, 4, 5 are only cleared by the clear staus register command, in cases where multiple bytes are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes suspend erase suspend erase loop 1 0 standby command erase setup erase confirm comments data = 20h addr = within block to be erased data = d0h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = v pp low detect check sr.4,5 both 1 = command sequence error read status register data (see above) v pp range error command sequence error block erase successful sr.3 = sr.4,5 = 1 0 1 0 block erase error sr.5 = 1 0 attempted erase of locked block - aborted sr.1 = 1 0 read status register data toggle ce# or oe# to update status register data standby check sr.5 1 = block erase error standby check sr.1 1 = attempted erase of locked block - erase aborted 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 49 0645_15 figure 18. erase suspend/resume flowchart start write b0h read status register no comments data = b0h addr = x data = ffh addr = x sr.7 = sr.6 = 1 write ffh read array data erase completed done reading yes write ffh write d0h erase resumed read array data 0 1 read array data from block other than the one being erased. status register data toggle ce# or oe# to update status register data addr = x check sr.7 1 = wsm ready 0 = wsm busy check sr.6 1 = erase suspended 0 = erase completed data = d0h addr = x bus operation write standby write read standby read command 0 write 70h status register data toggle ce# or oe# to update status register data addr = x write write data = 70h addr = x command erase suspend read status read array erase resume 3 volt intel ? advanced+ boot block flash memory stacked-csp family 50 datasheet 0645_16 figure 19. locking operations flowchart start write 60h (configuration setup) no comments data = 60h addr = x write 90h (read configuration) read block lock status locking change confirmed? locking change complete bus operation write command write 01h, d0h, or 2fh write write data= 01h (lock block) d0h (unlock block) 2fh (lockdown block) addr=within block to lock command config. setup lock, unlock, or lockdown data = 90h addr = x write (optional) read configuration block lock status data addr = second addr of block read (optional) block lock status confirm locking change on dq 1 , dq 0 . (see block locking state table for valid combinations.) standby (optional) optional write ffh (read array) 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 51 0645_17 figure 20. protection register programming flowchart start write c0h (protection reg. program setup) write protect. register address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pp range error protection register programming error attempted program to locked register - aborted program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = full status check procedure bus operation write write standby protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1, 1 0,1 1,1 command protection program setup protection program comments data = c0h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments sr.1 sr.3 sr.4 0 1 1 v pp low 0 0 1 prot. reg. prog. error 1 0 1 register locked: aborted read status register data toggle ce# or oe# to update status register data standby 3 volt intel ? advanced+ boot block flash memory stacked-csp family 52 datasheet appendix b cfi query structure this appendix defines the data structure or ?database? returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. b.1 query structure output the query ?database? allows system software to gain information for controlling the flash component. this section describes the device?s cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest-order data outputs (dq 0-7 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, ?q? and ?r? in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. thus, the device outputs ascii ?q? in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ). at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the ?h? suffix has been dropped. in addition, since the upper byte of word-wide devices is always ?00h,? the leading ?00? has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. table 20. summary of query structure output as a function of device and mode device hex offset code ascii value device address 10: 51 ?q? 11: 52 ?r? 12: 59 ?y? 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 53 b.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or ?database.? the structure sub-sections and address locations are summarized below. table 21. example of query structure output of x16 and x8 devices word addressing byte addressing offset hex code value offset hex code value a 15 ?a 0 d 15 ?d 0 a 7 ?a 0 d 7 ?d 0 0010h 0051 ?q? 10h 51 ?q? 0011h 0052 ?r? 11h 52 ?r? 0012h 0059 ?y? 12h 59 ?y? 0013h p_idlo prvendor 13h p_idlo prvendor 0014h p_idhi id # 14h p_idlo id # 0015h plo prvendor 15h p_idhi id # 0016h phi tbladr 16h ... ... 0017h a_idlo altvendor 17h 0018h a_idhi id # 18h ... ... ... ... table 22. query structure offset sub-section name description notes 00h manufacturer code 1 01h device code 1 (ba+2)h block status register block-specific information 1,2 04-0fh reserved reserved for vendor-specific information 1 10h cfi query identification string command set id and vendor data offset 1 1bh system interface information device timing & voltage information 1 27h device geometry definition flash device layout 1 p primary intel - specific extended query ta bl e vendor - defined additional information specific to the primary vendor algorithm 1,3 notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = the beginning location of a block address (e.g., 08000h is the beginning location of block 1 when the block size is 32 kword). 3. offset 15 defines ?p? which points to the primary intel - specific extended query table. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 54 datasheet b.3 block lock status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the v cc supply was not accidentally removed during an erase operation. this bit is only reset by issuing another erase operation to the block. the block status register is accessed from word address 02h within each block. b.4 cfi query identification string the identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 23. block status register offset length description address value notes (ba+2)h 1 block lock status register ba+2: --00 or --01 1 bsr.0 block lock status 0 = unlocked 1 = locked ba+2: (bit 0): 0 or 1 bsr.1 block lock-down status 0 = not locked down 1 = locked down ba+2: (bit 1): 0 or 1 bsr 2?7: reserved for future use ba+2: (bit 2?7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is the beginning location of block 1 in word mode.) table 24. cfi identification offset length description addr. hex code value 10h 3 query-unique ascii string ?qry? 10 --51 ?q? 11: - -52 ?r ? 12: --59 ?y? 13h 2 primary vendor command set and control interface id code. 13: --03 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --35 16: --00 17h 2 alternate vendor command set and control interface id code 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 55 b.5 system interface information table 25. system interface information offset length description addr. hex code value 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.3 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --b4 11.4 v 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --c6 12.6 v 1fh 1 ?n? such that typical single word program time-out = 2 n s 1f: --05 32 s 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.3 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --b4 11.4 v 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1e: --c6 12.6 v 1fh 1 ?n? such that typical single word program time-out = 2 n s 1f: --05 32 s 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 bcd volts 1c: --36 3.3 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100 mv bits 4?7 hex volts 1d: --b4 11.4 v 20h 1 ?n? such that typical max. buffer write time-out = 2 n s 20: --00 n/a 21h 1 ?n? such that typical block erase time-out = 2 n ms 21: --0a 1 s 22h 1 ?n? such that typical full chip erase time-out = 2 n ms 22: --00 n/a 23h 1 ?n? such that maximum word program time-out = 2 n times typical 23: --04 512 s 24h 1 ?n? such that maximum buffer write time-out = 2 n times typical 24: --00 n/a 25h 1 ?n? such that maximum block erase time-out = 2 n times typical 25: --03 8 s 26h 1 ?n? such that maximum chip erase time-out = 2 n times typical 26: --00 na 3 volt intel ? advanced+ boot block flash memory stacked-csp family 56 datasheet b.6 device geometry definition n table 26. device geometry definition offset length description code see table below 27h 1 ?n? such that device size = 2 n in number of bytes 27: 28h 2 flash device interface: x8 async x16 async x8/x16 async 28: --01 x16 28:00,29:00 28:01,29:00 28:02,29:00 29: --00 2ah 2 ?n? such that maximum number of bytes in write buffer = 2 n 2a: --00 0 2b: --00 2ch 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --02 2 2dh 4 erase block region 1 information 2d: bits 0?15 = y, y+1 = number of identical-size erase blocks 2e: bits 16?31 = z, region erase block(s) size are z x 256 bytes 2f: 30: 31h 4 erase block region 2 information 31: bits 0?15 = y, y+1 = number of identical-size erase blocks 32: bits 16?31 = z, region erase block(s) size are z x 256 bytes 33: 34: device geometry definition address 16-mbit 32-mbit ?b ?t ?b ?t 27: --15 --15 --16 --16 28: --01 --01 --01 --01 29: --00 --00 --00 --00 2a: --00 --00 --00 --00 2b: --00 --00 --00 --00 2c: --02 --02 --02 --02 2d: --07 --1e --07 --3e 2e: --00 --00 --00 --00 2f: --20 --00 --20 --00 30: --00 --01 --00 --01 31: --1e --07 --3e --07 32: --00 --00 --00 --00 33: --00 --20 --00 --20 34: --01 --00 --01 --00 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 57 b.7 intel-specific extended query table certain flash features and commands are optional. the intel - specific extended query table specifies this and other similar types of information. table 27. primary-vendor specific extended query offset (1) p = 35h length description (optional flash features and commands) addr. hex code value (p+0)h 3 primary extended query table 35: --50 ?p? (p+1)h unique ascii string ?pri? 36: --52 ?r? (p+2)h 37: --49 ?i? (p+3)h 1 major version number, ascii 38: --31 ?1? (p+4)h 1 minor version number, ascii 39: --30 ?0? (p+5)h 4 optional feature and command support (1=yes, 0=no) 3a: --66 (p+6)h bits 9?31 are reserved; undefined bits are ?0.? if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. 3b: --00 (p+7)h 3c: --00 (p+8)h 3d: --00 bit 0 chip erase supported bit 0 = 0no bit 1 suspend erase supported bit 1 = 1yes bit 2 suspend program supported bit 2 = 1yes bit 3 legacy lock/unlock supported bit 3 = 0no bit 4 queued erase supported bit 4 = 0no bit 5 instant individual block locking supported bit 5 = 1yes bit 6 protection bits supported bit 6 = 1yes bit 7 page mode read supported bit 7 = 0no bit 8 synchronous read supported bit 8 = 0no (p+9)h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1?7 reserved; undefined bits are ?0? 3e: --01 bit 0 program supported after erase suspend bit 0 = 1yes (p+a)h 2 block status register mask 3f: --03 (p+b)h bits 2?15 are reserved; undefined bits are ?0? 40: --00 bit 0 block lock-bit status register active bit 0 = 1yes bit 1 block lock-down bit status active bit 1 = 1yes (p+c)h 1 v cc logic supply highest performance program/erase voltage bits 0?3 bcd value in 100 mv bits 4?7 bcd value in volts 41: --33 3.3 v (p+d)h 1 v pp optimum program/erase supply voltage bits 0?3 bcd value in 100 mv bits 4?7 hex value in volts 42: --c0 12.0 v 3 volt intel ? advanced+ boot block flash memory stacked-csp family 58 datasheet table 28. protection register information offset (1) p = 35h length description (optional flash features and commands) addr. hex code value (p+e)h 1 number of protection register fields in jedec id space. ?00h,? indicates that 256 protection bytes are available 43: --01 01 (p+f)h 4 protection field 1: protection description 44: --80 80h (p+10)h this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device- unique serial numbers. others are user programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory pre-programmed and user-programmable. 45: --00 00h (p+11)h bits 0?7 = lock/bytes jedec-plane physical low address bits 8?15 = lock/bytes jedec -plane physical high address bits 16?23 = ?n? such that 2 n = factory pre- programmed bytes bits 24?31 = ?n? such that 2 n = user programmable bytes 46: --03 8 byte (p+12)h 47: --03 8 byte (p+13)h reserved for future use 48: note: 1. the variable p is a pointer which is defined at cfi offset 15h. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 59 appendix c word-wide memory map diagrams 16-mbit, 32-mbit 64-mbit [future], word-wide memory addressing top boot bottom boot size (kw) 16-mbit 32-mbit 64-mbit size (kw) 16-mbit 32-mbit 64-mbit 4 ff000-fffff 1ff000-1fffff 3ff000-3fffff 32 3f8000-3fffff 4 fe000-fefff 1fe000-1fefff 3fe000-3fefff 32 3f0000-3f7fff 4 fd000-fdfff 1fd000-1fdfff 3fd000-3fdfff 32 3e8000-3effff 4 fc000-fcfff 1fc000-1fcfff 3fc000-3fcfff 32 3e0000-3e7fff 4 fb000-fbfff 1fb000-1fbfff 3fb000-3fbfff 32 3d8000-3dffff 4 fa000-fafff 1fa000-1fafff 3fa000-3fafff 32 3d0000-3d7fff 4 f9000-f9fff 1f9000-1f9fff 3f9000-3f9fff 32 3c8000-3cffff 4 f8000-f8fff 1f8000-1f8fff 3f8000-3f8fff 32 3c0000-3c7fff 32 f0000-f7fff 1f0000-1f7fff 3f0000-3f7fff 32 3b8000-3bffff 32 e8000-effff 1e8000-1effff 3e8000-3effff 32 3b0000-3b7fff 32 e0000-e7fff 1e0000-1e7fff 3e0000-3e7fff 32 3a8000-3affff 32 d8000-dffff 1d8000-1dffff 3d8000-3dffff 32 3a0000-3a7fff 32 d0000-d7fff 1d0000-1d7fff 3d0000-3d7fff 32 398000-39ffff 32 c8000-cffff 1c8000-1cffff 3c8000-3cffff 32 390000-397fff 32 c0000-c7fff 1c0000-1c7fff 3c0000-3c7fff 32 388000-38ffff 32 b8000-bffff 1b8000-1bffff 3b8000-3bffff 32 380000-387fff 32 b0000-b7fff 1b0000-1b7fff 3b0000-3b7fff 32 378000-37ffff 32 a8000-affff 1a8000-1affff 3a8000-3affff 32 370000-377fff 32 a0000-a7fff 1a0000-1a7fff 3a0000-3a7fff 32 368000-36ffff 32 98000-9ffff 198000-19ffff 398000-39ffff 32 360000-367fff 32 90000-97fff 190000-197fff 390000-397fff 32 358000-35ffff 32 88000-8ffff 188000-18ffff 388000-38ffff 32 350000-357fff 32 80000-87fff 180000-187fff 380000-387fff 32 348000-34ffff 32 78000-7ffff 178000-17ffff 378000-37ffff 32 340000-347fff 32 70000-77fff 170000-177fff 370000-377fff 32 338000-33ffff 32 68000-6ffff 168000-16ffff 368000-36ffff 32 330000-337fff 32 60000-67fff 160000-167fff 360000-367fff 32 328000-32ffff 32 58000-5ffff 158000-15ffff 358000-35ffff 32 320000-327fff 32 50000-57fff 150000-157fff 350000-357fff 32 318000-31ffff 32 48000-4ffff 148000-14ffff 348000-34ffff 32 310000-317fff 32 40000-47fff 140000-147fff 340000-347fff 32 308000-30ffff 32 38000-3ffff 138000-13ffff 338000-33ffff 32 300000-307fff 32 30000-37fff 130000-137fff 330000-337fff 32 2f8000-2fffff 32 28000-2ffff 128000-12ffff 328000-32ffff 32 2f0000-2f7fff 32 20000-27fff 120000-127fff 320000-327fff 32 2e8000-2effff 32 18000-1ffff 118000-11ffff 318000-31ffff 32 2e0000-2e7fff 32 10000-17fff 110000-117fff 310000-317fff 32 2d8000-2dffff 32 08000-0ffff 108000-10ffff 308000-30ffff 32 2d0000-2d7fff 32 00000-07fff 100000-107fff 300000-307fff 32 2c8000-2cffff 32 0f8000-0fffff 2f8000-2fffff 32 2c0000-2c7fff 32 0f0000-0f7fff 2f0000-2f7fff 32 2b8000-2bffff 32 0e8000-0effff 2e8000-2effff 32 2b0000-2b7fff 32 0e0000-0e7fff 2e0000-2e7fff 32 2a8000-2affff 32 0d8000-0dffff 2d8000-2dffff 32 2a0000-2a7fff 32 0d0000-0d7fff 2d0000-2d7fff 32 298000-29ffff 32 0c8000-0cffff 2c8000-2cffff 32 290000-297fff 32 0c0000-0c7fff 2c0000-2c7fff 32 288000-28ffff 32 0b8000-0bffff 2b8000-2bffff 32 280000-287fff 32 0b0000-0b7fff 2b0000-2b7fff 32 278000-27ffff 32 0a8000-0affff 2a8000-2affff 32 270000-277fff this column continues on next page this column continues on next page 3 volt intel ? advanced+ boot block flash memory stacked-csp family 60 datasheet 16-mbit, 32-mbit, and 64-mbit [future], word-wide memory addressing top boot bottom boot size (kw) 16-mbit 32-mbit 64-mbit size (kw) 16-mbit 32-mbit 64-mbit 32 0a0000-0a7fff 2a0000-2a7fff 32 268000-26ffff 32 098000-09ffff 298000-29ffff 32 260000-267fff 32 090000-097fff 290000-297fff 32 258000-25ffff 32 088000-08ffff 288000-28ffff 32 250000-257fff 32 080000-087fff 280000-287fff 32 248000-24ffff 32 078000-07ffff 278000-27ffff 32 240000-247fff 32 070000-077fff 270000-277fff 32 238000-23ffff 32 068000-06ffff 268000-26ffff 32 230000-237fff 32 060000-067fff 260000-267fff 32 228000-22ffff 32 058000-05ffff 258000-25ffff 32 220000-227fff 32 050000-057fff 250000-257fff 32 218000-21ffff 32 048000-04ffff 248000-24ffff 32 210000-217fff 32 040000-047fff 240000-247fff 32 208000-20ffff 32 038000-03ffff 238000-23ffff 32 200000-207fff 32 030000-037fff 230000-237fff 32 1f8000-1fffff 1f8000-1fffff 32 028000-02ffff 228000-22ffff 32 1f0000-1f7fff 1f0000-1f7fff 32 020000-027fff 220000-227fff 32 1e8000-1effff 1e8000-1effff 32 018000-01ffff 218000-21ffff 32 1e0000-1e7fff 1e0000-1e7fff 32 010000-017fff 210000-217fff 32 1d8000-1dffff 1d8000-1dffff 32 008000-00ffff 208000-21ffff 32 1d0000-1d7fff 1d0000-1d7fff 32 000000-007fff 200000-207fff 32 1c8000-1cffff 1c8000-1cffff 32 1f8000-1fffff 32 1c0000-1c7fff 1c0000-1c7fff 32 1f0000-1f7fff 32 1b8000-1bffff 1b8000-1bffff 32 1e8000-1effff 32 1b0000-1b7fff 1b0000-1b7fff 32 1e0000-1e7fff 32 1a8000-1affff 1a8000-1affff 32 1d8000-1dffff 32 1a0000-1a7fff 1a0000-1a7fff 32 1d0000-1d7fff 32 198000-19ffff 198000-19ffff 32 1c8000-1cffff 32 190000-197fff 190000-197fff 32 1c0000-1c7fff 32 188000-18ffff 188000-18ffff 32 1b8000-1bffff 32 180000-187fff 180000-187fff 32 1b0000-1b7fff 32 178000-17ffff 178000-17ffff 32 1a8000-1affff 32 170000-177fff 170000-177fff 32 1a0000-1a7fff 32 168000-16ffff 168000-16ffff 32 198000-19ffff 32 160000-167fff 160000-167fff 32 190000-197fff 32 158000-15ffff 158000-15ffff 32 188000-18ffff 32 150000-157fff 150000-157fff 32 180000-187fff 32 148000-14ffff 148000-14ffff 32 178000-17ffff 32 140000-147fff 140000-147fff 32 170000-177fff 32 138000-13ffff 138000-13ffff 32 168000-16ffff 32 130000-137fff 130000-137fff 32 160000-167fff 32 128000-12ffff 128000-12ffff 32 158000-15ffff 32 120000-127fff 120000-127fff 32 150000-157fff 32 118000-11ffff 118000-11ffff 32 148000-14ffff 32 110000-117fff 110000-117fff 32 140000-147fff 32 108000-10ffff 108000-10ffff 32 138000-13ffff 32 100000-107fff 100000-107fff 32 130000-137fff 32 f8000-fffff f8000-fffff f8000-fffff 32 128000-12ffff 32 f0000-f7fff f0000-f7fff f0000-f7fff 32 120000-127fff 32 e8000-effff e8000-effff e8000-effff 32 118000-11ffff 32 e0000-e7fff e0000-e7fff e0000-e7fff 32 110000-117fff 32 d8000-dffff d8000-dffff d8000-dffff 32 108000-10ffff 32 d0000-d7fff d0000-d7fff d0000-d7fff 32 100000-107fff 32 c8000-cffff c8000-cffff c8000-cffff 32 0f8000-0fffff 32 c0000-c7fff c0000-c7fff c0000-c7fff this column continues on next page this column continues on next page 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 61 16-mbit, 32-mbit, and 64-mbit word-wide memory addressing top boot bottom boot size (kw) 16-mbit 32-mbit 64-mbit size (kw) 16-mbit 32-mbit 64-mbit 32 0f0000-0f7fff 32 b8000-bffff b8000-bffff b8000-bffff 32 0e8000-0effff 32 b0000-b7fff b0000-b7fff b0000-b7fff 32 0e0000-0e7fff 32 a8000-affff a8000-affff a8000-affff 32 0d8000-0dffff 32 a0000-a7fff a0000-a7fff a0000-a7fff 32 0d0000-0d7fff 32 98000-9ffff 98000-9ffff 98000-9ffff 32 0c8000-0cffff 32 90000-97fff 90000-97fff 90000-97fff 32 0c0000-0c7fff 32 88000-8ffff 88000-8ffff 88000-8ffff 32 0b8000-0bffff 32 80000-87fff 80000-87fff 80000-87fff 32 0b0000-0b7fff 32 78000-7ffff 78000-7ffff 78000-7ffff 32 0a8000-0affff 32 70000-77fff 70000-77fff 70000-77fff 32 0a0000-0a7fff 32 68000-6ffff 68000-6ffff 68000-6ffff 32 098000-09ffff 32 60000-67fff 60000-67fff 60000-67fff 32 090000-097fff 32 58000-5ffff 58000-5ffff 58000-5ffff 32 088000-08ffff 32 50000-57fff 50000-57fff 50000-57fff 32 080000-087fff 32 48000-4ffff 48000-4ffff 48000-4ffff 32 078000-07ffff 32 40000-47fff 40000-47fff 40000-47fff 32 070000-077fff 32 38000-3ffff 38000-3ffff 38000-3ffff 32 068000-06ffff 32 30000-37fff 30000-37fff 30000-37fff 32 060000-067fff 32 28000-2ffff 28000-2ffff 28000-2ffff 32 058000-05ffff 32 20000-27fff 20000-27fff 20000-27fff 32 050000-057fff 32 18000-1ffff 18000-1ffff 18000-1ffff 32 048000-04ffff 32 10000-17fff 10000-17fff 10000-17fff 32 040000-047fff 32 08000-0ffff 08000-0ffff 08000-0ffff 32 038000-03ffff 4 07000-07fff 07000-07fff 07000-07fff 32 030000-037fff 4 06000-06fff 06000-06fff 06000-06fff 32 028000-02ffff 4 05000-05fff 05000-05fff 05000-05fff 32 020000-027fff 4 04000-04fff 04000-04fff 04000-04fff 32 018000-01ffff 4 03000-03fff 03000-03fff 03000-03fff 32 010000-017fff 4 02000-02fff 02000-02fff 02000-02fff 32 008000-00ffff 4 01000-01fff 01000-01fff 01000-01fff 32 000000-007fff 4 00000-00fff 00000-00fff 00000-00fff 3 volt intel ? advanced+ boot block flash memory stacked-csp family 62 datasheet appendix d device id table table 29. device id read configuration address and data item address data manufacturer code x16 00000 0089 device code 16-mbit x 16-t x16 00001 88c2 16-mbit x 16-b x16 00001 88c3 32-mbit x 16-t x16 00001 88c4 32-mbit x 16-b x16 00001 88c5 note: other locations within the configuration address space are reserved by intel for future use. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 63 appendix e protection register addressing table 30. protection register addressing word-wide protection register addressing wordusea7a6a5a4a3a2a1a0 lockboth10000000 0factory10000001 1factory10000010 2factory10000011 3factory10000100 4user10000101 5user10000110 6user10000111 7user10001000 note: all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a 21? a 8 = 0. 3 volt intel ? advanced+ boot block flash memory stacked-csp family 64 datasheet appendix f mechanical and shipping media details f.1 mechanical specification note: shaded pins indicate upper address balls for 64-mbit and 128-mbit devices. in all flash and sram combinations, 66 balls are populated on lower density devices. (upper address balls are not populated). figure 21. stacked-csp: 12 x 8 ball matrix e 1 2 3 4 5 6 7 8 a b c d e f g h 9 10 11 12 a1 index d 1 2 3 4 5 6 7 8 a b c d e f g h 9 10 11 12 s2 s1 b e bottom view - ball up top view - ball down a a2 y a1 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 65 table 31. packaging specifications (0.18m and 0.25m) millimeters inches sym min nom max min nom max package height a 1. 400 0.0551 ball height a1 0.250 0.0098 package body thickness a2 0.960 0.0378 ball lead diameter b 0.350 0.400 0.450 0.0138 0.0157 0.0177 package body length ? 16-mbit/2-mbit d 9.900 10.00 10.100 0.3898 0.3937 0.3976 package body length ? 32-mbit/4-mbit, 16-mbit/4-mbit 11.900 12.000 12.100 0.4685 0.4724 0.4764 package body length ? 32-mbit/8-mbit 13.900 14.000 14.100 0.5472 0.5512 0.5551 package body width ? 16-mbit/2-mbit, 16-mbit/4-mbit, 32-mbit/4-mbit, 32-mbit/8-mbit e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 66 66 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along e 16-mbit/2-mbit, 16-mbit/4-mbit, 32-mbit/4-mbit, 32-mbit/8-mbit s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 distance along d 16-mbit/2-mbit s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 corner to ball a1 distance along d 32-mbit/4-mbit, 16-mbit/4-mbit 1.500 1.600 1.700 0.0591 0.0630 0.0669 corner to ball a1 distance along d 32-mbit/8-mbit 2.500 2.600 2.700 0.0984 0.1024 0.1063 3 volt intel ? advanced+ boot block flash memory stacked-csp family 66 datasheet table 32. packaging specifications (0.13m) millimeters inches sym min nom max min nom max package height 16/02-mb, 16/04-mb, 32/08-mb a 1. 200 0.0472 package height 32/04-mb 1. 400 0.0551 ball height 16/02-mb, 16/04-mb, 32/08-mb a1 0.200 0.0079 ball height 32/04-mb 0.250 0.0098 package body thickness 16/02-mb, 16/04-mb, 32/08-mb a2 0.860 0.0339 package body thickness 32/04-mb 0.960 0.0378 ball (lead) width 16/02-mb, 16/04-mb, 32/08-mb b 0.325 0.375 0.425 0.0128 0.0148 0.0167 ball (lead) width 32/04-mb 0.350 0.40 0.450 0.0138 0.0157 0.0177 package body length 16/02-mb, 16/04-mb d 9.900 10.000 10.100 0.3898 0.3937 0.3976 package body length 32/04-mb, 32/08-mb 11.900 12.000 12.100 0.4685 0.4724 0.4764 package body width 16/02-mb, 16/04-mb, 32/04-mb, 32/08-mb e 7.900 8.000 8.100 0.3110 0.3150 0.3189 pitch e 0.800 0.0315 ball (lead) count n 66 66 seating plane coplanarity y 0.100 0.0039 corner to ball a1 distance along e 16/02-mb, 16/04-mb, 32/04-mb, 32/08-mb s1 1.100 1.200 1.300 0.0433 0.0472 0.0512 corner to ball a1 distance along d 16/02-mb, 16/04-mb s2 0.500 0.600 0.700 0.0197 0.0236 0.0276 corner to ball a1 distance along d 32/04-mb, 32/08-mb s2 1.500 1.600 1.700 0.0591 0.0630 0.0669 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 67 f. 2 m e d i a information note: drawing is not to scale and is only designed to show orientation of devices. figure 22. stacked-csp device in tray orientation (8 mm x 10 mm and 8 mm x 12 mm device pin 1 tray chamfer figure 23. stacked-csp device in 24 mm tape (8 mm x 10 mm and 8 mm x 12 mm) device pin 1 3 volt intel ? advanced+ boot block flash memory stacked-csp family 68 datasheet appendix g additional information order number document/tool 292216 ap-658 designing for upgrade to the advanced+ boot block flash memory 292215 ap-657 designing with the advanced+ boot block flash memory architecture contact your intel representative flash data integrator (fdi) software developer?s kit 297874 fdi interactive: play with intel?s flash data integrator on your pc notes: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intel?s world wide web home page at http://www.intel.com or http://developer.intel.com for technical documentation and tools. 3 volt intel ? advanced+ boot block flash memory stacked-csp family datasheet 69 appendix h ordering information table 33. ordering information for 0.25 m and 0.18 m . table 34. ordering information for combinations with 16m 0.13 m flash r d 2 8 f 3 2 0 8 c 3 t 7 0 package rd = 8x12 ball matrix csp product line designator flash density 320 = x16 (32 mbit) 160 = x16 (16 mbit) sram device density 16 mbit = 70, 90, 110 32 mbit = 70, 90 access speed (ns) t = top blocking b = bottom blocking product family c3 = 3 v advanced+ boot block v cc = 2.7 v - 3.3 v v pp = 1.65 v - 3.3 v or 11.4 v - 12.6 v for all intel flash products ? 8 = x16 (8 mbit) 4 = x16 (4 mbit) 2 = x16 (2 mbit) r d 2 8 f 1 6 0 2 c 3 t d 7 0 package rd = stacked-csp product line designator 16 mbit = 70 ns access speed (ns) 38f = intel flash stacked memory ? flash density 320 = x16 (32 mbit) 160 = x16 (16 mbit) sram device density 4 = x16 (4 mbit) 2 = x16 (2 mbit) parameter location t = top blocking b = bottom blocking d = 0.13m technology differentiator c = advanced+ boot block flash memory product family 3 volt intel ? advanced+ boot block flash memory stacked-csp family 70 datasheet table 35. ordering information for combinations with 32m 0.13 m flash r d 3 8 f 1 0 1 0 c 0 z t l 0 package rd = stacked-csp product line designator density flash #1 = 1 = 32 mbit flash #2 = 0 = no die flash #3 = 1 = 4 mbit sram = 2 = 8 mbit sram flash #4 = 0 = no die product family 0 = original version of this product: flash speed = 70 ns flash process = 0.13 m vccq = 2.7 v to 3.3 v device details l = 72 ball "i"-ballout pinout indicator parameter location t = top blocking b = bottom blocking voltage z = 3.0v i/o c = advanced+ boot block flash memory 38f = intel flash stacked memory ? table 36. ordering information valid combinations 0.25m c3 stacked-csp 0.18m c3 stacked-csp 0.13m c3 stacked-csp 32-mbit no longer available. rd28f3208c3t70 rd28f3208c3b70 rd28f3208c3t90 rd28f3208c3b90 rd28f3204c3t70 rd28f3204c3b70 rd38f1010c0ztl0 RD38F1010C0ZBL0 rd38f1020c0ztl0 rd38f1020c0zbl0 16-mbit rd28f1604c3t90 rd28f1604c3b90 rd28f1604c3t110 rd28f1604c3b110 rd28f1602c3t90 rd28f1602c3b90 rd28f1602c3t110 rd28f1602c3b110 rd28f1602c3t70 rd28f1602c3b70 rd28f1602c3td70 rd28f1602c3bd70 rd28f1604c3td70 rd28f1604c3bd70 |
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